KHALIL-HANI, M.; SHAIKH-HUSIN, N. An Optimization Algorithm Based On Grid-Graphs For Minimizing Interconnect Delay In VLSI Layout Design. Malaysian Journal of Computer Science, [S. l.], v. 22, n. 1, p. 19–33, 2009. Disponível em: http://jice.um.edu.my/index.php/MJCS/article/view/6351. Acesso em: 23 dec. 2024.